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Analog Devices Inc. AD9545BCPZ

Manufacturer Part Number : AD9545BCPZ
Manufacturer : Analog Devices Inc.
Description : 2.4GHz, 750Mhz Clock Synchroniser
Lead Free Status / RoHS Status : Lead free / RoHS Compliant
Datasheet : AD9545BCPZ.PDF AD9545BCPZ PDF
EDA / CAD Models : AD9545BCPZ by SnapEDA
Quantity:
1 60 7192088 /datasheets/IntegratedCircuits/AD9545BCPZ-3379294.pdf Analog-Devices-Inc/AD9545BCPZ 7192088
Type:Clock Synchronizer
PLL:Yes
Input:Differential or Single-Ended
Output:CML, HCSL, LVDS or Single-Ended
Frequency - Max:2.4GHz
Divider/Multiplier:Yes/Yes
Voltage - Supply:1.71 V ~ 3.465 V
Operating Temperature:-40~C ~ 85~C
Mounting Type:Surface Mount
Package / Case:48-WFQFN Exposed Pad
Supplier Device Package:48-LFCSP (7x7)

The AD9545BCPZ supports existing and emerging International Telecommunications Union (ITU) standards for the delivery of frequency, phase, and time of day over service provider packet networks, including ITU-G.8262, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2.

AD9545BCPZ

The AD9545BCPZ is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the −40°C to +85°C temperature range.

AD9545BCPZ pin configuration diagram

AD9545BCPZ pin configuration diagram

Application

  • Global positioning system (GPS)

  • PTP (IEEE 1588)

  • Synchronous Ethernet (SyncE) jitter cleanup and synchronization Optical transport networks (OTN)

  • Synchronous digital hierarchy (SDH), and macro and small cell base stations

  • JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking

Features

  • Dual DPLL synchronizes 1 Hz to 750 MHz physical layer clocks, providing frequency translation with jitter cleaning of noisy references

  • Complies with ITU-T G.8262 and Telcordia GR-253

  • Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2

  • Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb (5 × 10−8)

  • Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus

  • Programmable digital loop filter bandwidth: 10−4Hz to 1850Hz

  • 2 differential or 4 single-ended input references

  • Crosspoint mux interconnects reference inputs to PLLs

  • Supports embedded (modulated) input/output clock signals

  • Fast DPLL locking modes

Request for Quotation

Technical Parameters of AD9545BCPZ

Type:Clock Synchronizer
PLL:Yes
Input:Differential or Single-Ended
Output:CML, HCSL, LVDS or Single-Ended
Frequency - Max:2.4GHz
Divider/Multiplier:Yes/Yes
Voltage - Supply:1.71 V ~ 3.465 V
Operating Temperature:-40~C ~ 85~C
Mounting Type:Surface Mount
Package / Case:48-WFQFN Exposed Pad
Supplier Device Package:48-LFCSP (7x7)

Product Details

The AD9545BCPZ supports existing and emerging International Telecommunications Union (ITU) standards for the delivery of frequency, phase, and time of day over service provider packet networks, including ITU-G.8262, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2.

AD9545BCPZ

The AD9545BCPZ is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the −40°C to +85°C temperature range.

AD9545BCPZ pin configuration diagram

AD9545BCPZ pin configuration diagram

Application

  • Global positioning system (GPS)

  • PTP (IEEE 1588)

  • Synchronous Ethernet (SyncE) jitter cleanup and synchronization Optical transport networks (OTN)

  • Synchronous digital hierarchy (SDH), and macro and small cell base stations

  • JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking

Features

  • Dual DPLL synchronizes 1 Hz to 750 MHz physical layer clocks, providing frequency translation with jitter cleaning of noisy references

  • Complies with ITU-T G.8262 and Telcordia GR-253

  • Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2

  • Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb (5 × 10−8)

  • Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus

  • Programmable digital loop filter bandwidth: 10−4Hz to 1850Hz

  • 2 differential or 4 single-ended input references

  • Crosspoint mux interconnects reference inputs to PLLs

  • Supports embedded (modulated) input/output clock signals

  • Fast DPLL locking modes

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