Occamy Processor: A Powerful Chip for Aerospace Computing

The European Space Agency (ESA) is now backing the development of the Occamy processor, created by engineers from the Swiss Federal Institute of Technology Zurich and the University of Bologna. The processor features two chiplets, each with 216 32-bit RISC-V cores, an unknown number of 64-bit FPUs, and two 16GB HBM2e memory chips from Micron.

The processor's cores are interconnected through an intermediary layer, allowing the dual-CPU setup to deliver 0.75 FP64 TFLOPS of performance and 6 FP8 TFLOPS of computing power. Although the ESA and its development partners have not disclosed Occamy's power consumption, the chip reportedly employs passive cooling, indicating it may be a low-power processor. One advantage of the chiplet design is the ability to add more chiplets within the package, accelerating specific workloads when needed. Each Occamy chip contains 216 RISC-V cores and FPUs for matrix calculations, totaling around 1 billion transistors on a 73mm2 chip, manufactured using GlobalFoundries' 14LPP process.

For comparison, Intel's Alder Lake chip measures 163 mm2. In terms of performance, NVIDIA's A30 GPU has 24GB HBM2 memory, offering 5.2 FP64/10.3 FP64 Tensor TFLOPS and 330/660 (sparse) INT8 TOPS.

The Occamy CPU was primarily developed as part of the ESA's EuPilot program, one of many chips the agency is considering for aerospace computing applications.

According to reports, Occamy can simulate calculations on an FPGA, with implementation tested on two AMD Xilinx Virtex UltraScale+ HBM FPGAs and Virtex UltraScale+ VCU1525 FPGAs.

As shown in Figure 2, the 73mm^2 compute chiplet Occamy consists of six banks of four compute clusters, host CVA6, Rambus' HBM2e controller IP, and a source-synchronous serial DDR chip-to-chip link.

Figure 2

As shown in Figure 3, each Occamy compute chiplet combines 216 32-bit Snitch cores grouped in groups of four compute clusters with a linux-capable 64-bit CVA6 core actinv as the host controller. The DMA-enhanced snitch cores within the cluster can access HBM2e DRAM through a 512-bit latency-tolerant AXI interconnect.

Figure 3

Occamy's potential in aerospace computing holds great promise for the European Space Agency, as its low-power consumption and chiplet design offer increased flexibility and efficiency. The processor's compatibility with FPGA technology allows for further testing and optimization in various aerospace applications, making it a valuable asset in the EuPilot program.

The use of RISC-V cores in the Occamy processor signifies a growing trend towards open-source hardware in the technology industry. As the demand for customized, efficient, and cost-effective processors increases, more organizations are likely to adopt open-source architectures like RISC-V for their specialized needs.

As Occamy continues to be developed and tested, it will be interesting to see how the European Space Agency leverages its capabilities in future aerospace missions. The processor's low-power consumption, combined with its performance capabilities, makes it a viable option for spacecraft, satellites, and other space-based systems that require both energy efficiency and computational power.

In conclusion, the Occamy processor represents a significant advancement in aerospace computing. Its low-power design, FPGA compatibility, and use of RISC-V cores demonstrate the potential for greater efficiency and adaptability in future space missions. As the European Space Agency and its partners continue to explore the applications of Occamy within the EuPilot program, the processor may pave the way for more specialized, energy-efficient chips in the aerospace industry.